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4 sections20 entries

Semiconductor stock analysis: reading the cycle before repricing

Semiconductor analysis fails when investors use current earnings as if the cycle were frozen. The right order is: place the business in the cycle, stress the competitive position, then build a valuation that can survive the next inventory correction.

✓Write where you believe channel inventory sits relative to normal before you call the stock cheap on current earnings.
✓Decompose revenue growth into ASP and volume before extrapolating — price declines during oversupply can make volume growth look like revenue weakness.
✓Measure gross margin at trough in the last down cycle before forecasting normalized margins — the floor tells you more than the ceiling.
✓Identify whether the competitive position is built on process node leadership, IP, or customer lock-in — then ask how durable each is.
Go to frameworkSee a sample report
When to use this

Use this before initiating on any fabless chip designer, integrated device manufacturer, foundry, semiconductor equipment maker, or EDA software company. It is the research frame for understanding what cycle you are buying and what the business is worth through that cycle.

Why it matters now

The semiconductor industry has experienced a compressed boom-bust-recovery since 2020, with lead times swinging from 50+ weeks to near-normal in under three years. Investors who anchored on 2021-2022 peak earnings paid for it in 2023. The next re-rating will belong to those who read inventory signals before the earnings guide-down arrives.

Where theses break

The blueprint breaks when channel inventory is assumed to be lean because management says so rather than because distributor days on hand, customer inventory disclosures, and wafer start data confirm it; when design-win momentum is confused with near-term revenue visibility; and when through-cycle gross margin is modeled off peak rather than demonstrated mid-cycle levels.

Full framework

4 sections · 20 entries — work through each before you size a position.

Most weak semiconductor research mistakes a peak-cycle print for normalized earnings power. The strongest research starts by reading where channel inventories, utilization rates, and lead times sit relative to historical ranges — then asks which business models compound through the downturn rather than just participating in the upcycle.

20 entries in view

Understand the business model before you price the growth

Semiconductor companies look like a single sector on a screen but operate under fundamentally different economic models. The valuation framework must match the revenue architecture, cost structure, and competitive position — not just the end market.

Classify the business as fabless, IDM, foundry, equipment, or EDA before touching valuation

A fabless designer like NVIDIA outsources manufacturing, concentrates investment in IP and architecture, and earns gross margins above 70% because it does not carry factory overhead. An IDM like Texas Instruments owns the factory, earns pricing power through proprietary process nodes, but absorbs fixed costs on every downturn. A foundry earns on capacity utilization, not product differentiation. These are different businesses with different risk profiles and different valuation disciplines.

Why it matters

The most common valuation error in semiconductors is applying a fabless multiple to a business with IDM-level capital intensity or vice versa. Fixed-cost structure is the key separator.

When it matters

Before initiating any position and every time the company shifts its manufacturing strategy or announces a major capex plan.

Investor take

Write one sentence on what percentage of the business's revenue requires physical manufacturing capacity that it owns — that percentage determines how much of the bear case is driven by fixed-cost absorption rather than demand.

Separate product revenue from end-market demand at least two steps down the supply chain

A chip company's shipments reflect production decisions at OEMs and distributors, not necessarily end demand from consumers or enterprises. During upcycles, customers double-order and build buffer inventory. During corrections, they draw down that inventory without placing new orders. Revenue can fall 20-30% before end demand has moved at all. The business with the best end demand can have the worst near-term revenue if channel inventory is elevated.

Why it matters

The gap between chip company shipments and actual end demand at the device or system level is where inventory cycle analysis lives. Missing it is how investors buy into the correction instead of ahead of the recovery.

When it matters

Every time a company reports a quarter where shipment growth has materially outpaced the publicly reported growth of its largest end market by volume.

Investor take

Find the largest disclosed end market (PC, smartphone, data center, auto, industrial) and track the channel's reported inventory days alongside the chip company's reported revenue. A divergence of more than 20% for two or more quarters is a channel inventory signal.

Measure content-per-device growth as the structural revenue driver, separate from unit volume

End-unit volume growth for smartphones or PCs rarely exceeds low single digits over a cycle. But semiconductor revenue from those same units can grow 10-20% annually because each new device generation uses more chips — more memory, more power management, more connectivity, more compute. Content per device is the structural compounder inside the cyclical business. It is why semiconductor revenue tends to grow faster than the unit markets it serves.

Why it matters

Investors who focus on PC or smartphone unit volumes and conclude the semiconductor opportunity is capped are misreading the economics. The right question is how many more dollars of chip content each unit generation requires.

When it matters

When evaluating any semiconductor company tied to a mature hardware end market that appears ex-growth on unit volume basis.

Investor take

Break the revenue growth attribution into three buckets: unit volume growth, content growth per unit, and ASP change. If content growth is 15% and unit volume is flat, the long-run revenue story is intact regardless of short-term shipment data.

Understand customer concentration and design-win dependency before calling the revenue durable

Fabless chip companies often generate 20-40% of revenue from a single customer. If that customer is Apple, Qualcomm, or a hyperscaler, a platform shift, internal chip development, or sourcing diversification can permanently impair the revenue base. Design wins provide visibility — a chip designed into a product generates revenue for that product's life — but new product cycles create reset risk when the replacement design uses a different supplier.

Why it matters

Customer concentration above 30% from a single account creates a structural risk that deserves explicit modeling in the bear case, not a footnote. Internal chip development at large OEMs has displaced external suppliers multiple times in the last decade.

When it matters

Before initiating any position where a single disclosed customer represents more than 15% of revenue, and every time the key customer announces a new product platform or signals interest in developing in-house chips.

Investor take

Model the scenario where the top customer reduces purchases by 30% over 24 months and calculate the revenue, gross margin, and FCF impact. That exercise usually reveals whether the current valuation prices that risk or ignores it.

Assess the product mix shift from legacy nodes to leading-edge or specialized nodes

A semiconductor company transitioning from mature 28nm or 40nm production to 5nm or 3nm leading-edge nodes is going through a cost and competitive inflection that changes both gross margin and competitive positioning. Similarly, a company shifting toward automotive, industrial, or defense end markets from consumer electronics is extending product cycles and improving pricing stability, but at the cost of longer design-win ramps and more volatile annual volumes.

Why it matters

Product mix shifts often arrive before they appear in reported revenue — design wins, customer qualification disclosures, and R&D spending shifts are the leading indicators.

When it matters

When evaluating any semiconductor company that has announced a major process node transition, a new end market expansion, or a significant manufacturing partnership or outsourcing decision.

Investor take

Track R&D investment by product line or end market when disclosed. A company accelerating R&D toward automotive or AI inference chips is telegraphing where revenue mix is headed in 3-5 years. That forward mix deserves a different gross margin assumption than the current one.

Read the cycle from supply chain signals before the earnings print tells you

The semiconductor cycle is one of the most predictable in industrials — not because it is easy to time, but because the signals precede the revenue inflection by several quarters for those who track the right data.

Use book-to-bill as a leading demand indicator, not a current-period revenue predictor

Book-to-bill above 1.0 means new orders placed exceed current shipments — a signal that demand is running ahead of supply. Below 1.0, the reverse: shipments are outpacing orders, which typically means customers have enough inventory to draw from and are not replenishing. The SIA publishes industry-level data monthly. Company-level disclosures in the earnings transcript, while less precise, often signal the direction before the shipment data confirms it.

Why it matters

Book-to-bill leads revenue by 1-3 quarters on both the upswing and the correction. Investors who wait for revenue confirmation are typically buying into the recovery well after the stock has moved.

When it matters

Every quarter when evaluating whether order momentum is accelerating or decelerating, and when building a 4-8 quarter revenue bridge.

Investor take

If a company's book-to-bill has fallen below 1.0 for two consecutive quarters and management has not revised guidance downward, assume the revenue guide will follow. The question is timing, not direction.

Track channel inventory days at distributors and key OEMs, not just at the chip company

The chip company's own inventory days are informative. The distribution channel's inventory days are more important. When distributor weeks-on-hand expands beyond the 5-year average, customers are working down stock before placing new orders. That destock can last 3-6 quarters and makes the chip company's shipments look worse than end demand actually is — which is also why it creates the best entry points once the destock is confirmed to be complete.

Why it matters

Channel inventory is the hidden variable that disconnects near-term revenue from long-run demand. Investors who ignore it buy the correction; those who track it buy the recovery.

When it matters

Every quarter, using distributor inventory data disclosed in 10-Q filings, sell-through vs. sell-in disclosures, and commentary from distributors like Arrow Electronics and Avnet about weeks-on-hand.

Investor take

Compare the chip company's reported days of inventory to its major distributors' disclosed inventory levels. If both are elevated, the correction is structural. If only the chip company's is elevated, it may be building production inventory for a demand recovery it sees that the channel does not yet reflect.

Monitor capacity utilization across foundry networks as a gross margin early warning system

For any IDM or foundry-dependent supply chain, capacity utilization is the direct input to gross margin. At 90%+ utilization, fixed costs spread across maximum output and margins approach peak. At 70% or below, gross margin can collapse by 8-15 percentage points as the same fixed cost base divides across fewer wafer starts. TSMC, GlobalFoundries, and UMC disclose utilization data or proxy data quarterly — it is the single best gross margin leading indicator for fabless companies dependent on those foundries.

Why it matters

A utilization drop from 90% to 75% can compress a foundry's gross margin from 55% to 45% in two quarters. For fabless companies that source from those foundries, the margin effect is smaller but still visible through higher cost per unit.

When it matters

When evaluating any IDM or foundry position, and when a major foundry has reported declining wafer starts in its latest investor day or earnings release.

Investor take

Build a gross margin sensitivity table: what does gross margin look like at 90%, 80%, and 70% utilization? That range is your realistic margin scenario set for the next 6-12 months, not management's guidance.

Track lead time compression as a correction pre-signal, not just a supply chain metric

When semiconductor lead times compress from 40+ weeks to 20 weeks to under 16 weeks, it means supply is catching up with or exceeding demand. Lead time compression typically precedes order cancellations and inventory build by 1-2 quarters, because customers who had been ordering aggressively to secure supply suddenly find themselves holding excess. The compression is visible in industry trackers, in procurement commentary from OEM 10-Qs, and sometimes directly in chip company investor presentations.

Why it matters

Lead time compression from peak levels is one of the clearest cycle-turn signals available before the revenue impact shows up. The companies that benefit most from extended lead times have the most to lose when those lead times normalize.

When it matters

When lead times for a specific product category — MCUs, power management ICs, analog — have been running above historical averages for 4+ quarters and are beginning to show the first signs of stabilization or decline.

Investor take

Track lead time data from the Susquehanna Financial Group's weekly lead time survey or equivalent industry sources. Map the lead time trend against the chip company's revenue trajectory for the same end market to understand the lag.

Separate end-demand growth from inventory-driven ordering in the revenue run-rate

During a chip shortage, OEMs order 1.3-1.5x their expected demand to secure supply. That excess ordering inflates reported revenue and backlog. When supply normalizes and customers stop double-ordering, reported revenue can fall 20-30% even though actual end demand has grown. Investors who extrapolate shortage-period revenue trajectories into the recovery consistently overpay. The discipline is to estimate what revenue would look like if order patterns were normalized — then compare that to current guidance.

Why it matters

The largest inventory corrections in semiconductor history — 1995-1996, 2001, 2008-2009, 2022-2023 — were all preceded by extended periods of double-ordering during supply tightness. The same mechanism repeats each cycle.

When it matters

Whenever reported backlog is growing meaningfully faster than the company's demonstrated capacity to ship, and whenever management is citing order strength as justification for a premium multiple.

Investor take

Ask: if the company's top 10 customers normalized their order books to reflect 1.0x actual demand rather than 1.3x security ordering, what would the revenue run-rate look like? Build that number before calling the current multiple justified.

Stress the competitive position with structural evidence, not process roadmap claims

Semiconductor competitive moats come from process node leadership, IP and architecture, customer lock-in through design wins, and switching costs embedded in the supply chain. Assessing which type of moat a company has — and how durable it is — determines whether a premium multiple is earned or assumed.

Distinguish process node leadership from manufacturing scale: they are different moats

TSMC's competitive advantage at 3nm and 2nm is a combination of process technology leadership, equipment relationships, and accumulated yield-learning data — not just scale. An IDM that manufactures at mature nodes (28nm, 40nm) competes on cost and customer relationships, not on technology. A fabless company that uses TSMC for leading-edge production has process access but no manufacturing moat — its competitive position rests entirely on architecture and IP.

Why it matters

Investors who attribute a manufacturing moat to a company that outsources its leading-edge production are counting a moat that belongs to the foundry, not to the chip designer.

When it matters

Whenever the thesis depends on sustained gross margin premium or pricing power tied to manufacturing differentiation.

Investor take

Map where the company manufactures by node. If 70%+ of revenue comes from products manufactured at a third-party foundry, the company's moat is IP and architecture — and the bear case should include what happens if a competitor designs a better chip on the same process node.

Use design-win pipeline coverage as a revenue visibility metric, not just a growth indicator

A design win locks a chip into a customer's bill of materials for the life of that product — typically 3-7 years for industrial and automotive, 2-3 years for consumer electronics. A design-win pipeline with 2-3x coverage relative to current revenue means the company can grow without winning new customers. One with less than 1x coverage relative to revenue means the business needs to keep winning to hold revenue flat.

Why it matters

Design-win coverage is the structural visibility metric that tells you whether revenue growth depends on execution the company can control or on winning deals in markets it does not yet serve.

When it matters

When evaluating any analog, mixed-signal, or application-specific chip company targeting automotive, industrial, or communications end markets where product cycles are long and switching costs are high.

Investor take

Ask management to disclose the value of design wins expected to generate revenue in the next 24 months versus current annual revenue. If that ratio is not disclosed, triangulate from the company's engineering headcount growth and R&D intensity — more engineers engaged in customer qualification usually implies growing design-win activity.

Assess R&D intensity relative to peers as a process and product roadmap predictor

Semiconductor companies that invest 15-20% of revenue in R&D are typically defending or building a process or architecture lead. Those that drop to 10-12% are either harvesting a mature product line or losing the pace competition. Analog Devices, Texas Instruments, and NVIDIA have sustained industry-leading ROIC partly because their R&D intensity has remained higher than commodity competitors for decades. A declining R&D intensity trend in a technology-dependent semiconductor business is a structural red flag.

Why it matters

R&D intensity is a leading indicator of competitive position 3-5 years forward. A competitor that doubles R&D spend while you hold it flat will win design cycles you cannot defend.

When it matters

Annually, and whenever a competitor announces a large R&D investment or a new architecture that competes with the company's roadmap.

Investor take

Build a peer R&D intensity table — R&D as a percentage of revenue for the last five years for the company and its three most relevant competitors. A widening gap in either direction is a competitive signal worth writing down before it shows up in market share data.

Evaluate geopolitical supply chain concentration as a scenario-weighted bear case, not a footnote

TSMC manufactures more than 90% of the world's most advanced logic chips. ASML is the sole supplier of extreme ultraviolet lithography machines. A geopolitical disruption to Taiwan or a change in export controls can impair the entire ecosystem simultaneously. This is not a remote scenario — it is the highest-consequence risk in the semiconductor industry and deserves explicit modeling, not a generic risk factor disclosure.

Why it matters

Supply chain concentration risk in semiconductors is structural and has been repriced by markets multiple times since 2020. The companies that benefit from reshoring and domestic capacity expansion — Intel, Micron, TSMC's Arizona fab — have a different risk profile than those entirely dependent on TSMC Taiwan.

When it matters

Before initiating any large-cap semiconductor position and whenever export control regulations change or U.S.-China trade policy shifts.

Investor take

Estimate the percentage of the company's revenue that depends on TSMC Taiwan capacity or on products that would be export-controlled under a tighter regulatory regime. That percentage is the ceiling on the geopolitical bear case impairment.

Test pricing power through ASP trends across product generations, not from management commentary

Semiconductor pricing power is real when ASPs hold or expand as a newer product generation replaces the previous one — meaning customers are willing to pay more for more capability. It is absent when ASPs decline at a rate faster than the cost-per-unit reduction from process improvement, which happens when competition commoditizes the product. Historical ASP trend by end market, when disclosed in segment data or derivable from units and revenue, is more informative than any management statement about competitive moat.

Why it matters

Commodity semiconductor markets (DRAM, NAND, standard logic) compete almost entirely on ASP and cost. Differentiated markets (analog, power management, RF, custom silicon) can sustain ASPs across product generations. The difference in gross margin over a cycle reflects this distinction.

When it matters

When building a long-run gross margin assumption and whenever a new competitor enters the relevant product category or a platform shift threatens to commoditize what was previously a differentiated product.

Investor take

Derive implied ASP per unit from revenue and disclosed unit shipments over four or more years. An upward ASP trend in a product category suggests real pricing power. A flat or declining trend suggests the product is being commoditized faster than the cost structure is improving.

Build a through-cycle valuation that survives the inventory correction

Semiconductor valuations that work are built on mid-cycle normalized earnings, not on peak-quarter prints. The companies worth owning at a premium are those that demonstrate ROIC well above cost of capital through the full cycle, not just at the top.

Anchor on mid-cycle gross margin, not peak-cycle — then build up from there

Peak semiconductor gross margins during upcycles often run 5-10 percentage points above mid-cycle levels because of full utilization, pricing power, and mix shift toward higher-value products. When the correction arrives, gross margin falls back to or below mid-cycle levels. Investors who underwrite peak gross margins as the steady state are paying for earnings power that does not survive the next inventory correction. Mid-cycle gross margin — typically observable from the midpoint of the last two full cycles — is the right anchor.

Why it matters

Peak gross margin is a cycle artifact, not an earnings quality signal. A 55% gross margin at 93% utilization tells you less about the business than a 47% gross margin at 78% utilization does. The latter shows you what the business earns when conditions are ordinary.

When it matters

Before initiating any position and when modeling 3-5 year earnings trajectories for any IDM, foundry, or capital-intensive chip company.

Investor take

Find the last three full inventory cycles in the historical financials. Average the gross margin at the midpoint of each upcycle phase. That average is your mid-cycle anchor. If current guidance implies gross margins 500+ basis points above that average, you are buying peak earnings.

Measure ROIC through the trough, not just at the peak, to judge the quality of the business

A semiconductor business with 25% ROIC at peak and 10% ROIC at trough, where WACC is 9%, is a structurally decent business — it earns above its cost of capital through the full cycle, even if not by much at trough. A business with 30% peak ROIC and 5% trough ROIC dips below its cost of capital at the bottom and deserves a lower through-cycle multiple, because shareholders are subsidizing the downturn. ROIC through the cycle is the honest quality test.

Why it matters

ROIC at the peak is what management talks about. ROIC at the trough is what the business actually earns when conditions are not favorable. The gap between peak and trough ROIC tells you how much the earnings stream depends on cycle timing versus structural competitive advantage.

When it matters

Annually, using at least 8-10 years of historical data that includes at least two full downcycles.

Investor take

Build a ROIC time series from annual 10-K data. Identify the peak, trough, and mid-cycle ROIC for each observable cycle. The spread between peak and trough is the cycle sensitivity. A narrow spread (under 10 percentage points) suggests competitive advantages that hold through the downturn.

Model FCF conversion under trough conditions before sizing the position

Capital-intensive semiconductor businesses can generate strong EBITDA at peak while producing very little FCF when capex and working capital absorb the operating cash flow. At trough, when revenue falls and the company is still finishing a capacity expansion committed at the peak, FCF can turn deeply negative. Know the FCF conversion rate at trough before sizing any IDM, equipment, or foundry position — that calculation determines whether the company can self-fund the recovery or will need to dilute equity.

Why it matters

A semiconductor company with $1B of EBITDA and $900M of sustaining capex generates $100M of FCF in a normal environment. At trough with $700M EBITDA and $800M capex already committed, that business is FCF-negative. Leverage ratios that look manageable at the peak can become stressful at trough.

When it matters

Whenever a company has committed to a large capacity expansion at cycle peak, and when debt-to-EBITDA ratios look comfortable on current earnings but would deteriorate sharply on trough assumptions.

Investor take

Model the three-scenario FCF bridge: peak (current guidance), mid-cycle (75-80% utilization), and trough (65-70% utilization). Apply each to committed capex and interest expense. The trough scenario tells you whether the balance sheet can absorb the correction without a capital raise.

Apply valuation multiples to normalized earnings power, not trailing or current-period prints

P/E and EV/EBITDA multiples on trailing or current-quarter earnings are misleading at cycle inflection points. A semiconductor company trading at 15x trailing P/E at peak cycle earnings may be trading at 25x normalized P/E if those earnings are 40% above mid-cycle. Conversely, a company at 30x trailing P/E in a trough year may be trading at 12x normalized — creating a value entry that looks expensive on the surface. The market's ability to see through cycle noise is the edge that requires this normalization discipline.

Why it matters

The most reliable semiconductor entries happen when the stock looks expensive on peak trailing earnings and cheap on normalized trough earnings simultaneously — meaning the market has given up on a recovery that the supply chain data suggests is already beginning.

When it matters

When the stock price has already moved 30-50% off the trough and the trailing P/E looks stretched but channel inventory data suggests the correction is 80-90% complete.

Investor take

Calculate the stock's implied P/E on mid-cycle normalized EPS rather than on current or trailing EPS. If mid-cycle P/E is below the company's historical average mid-cycle multiple, the stock is cheap on normalized earnings. If it is above, the current price requires above-average cycle execution to justify.

Write the inventory correction bear case in units and margin impact before deciding the stock is cheap

The bear case for a semiconductor stock is not a macro recession scenario — it is an inventory correction scenario with a specific mechanism: channel inventory rises by X weeks-on-hand, orders fall by Y percent, utilization drops to Z percent, gross margin compresses by W percentage points, and FCF turns negative for N quarters. Writing that scenario in explicit numbers forces you to decide whether the current valuation provides enough margin of safety to absorb the bear case or whether the current price assumes a soft landing that the supply chain data does not yet confirm.

Why it matters

Generic bear cases ('demand slows and margins compress') are useless for decision-making. Specific bear cases with quantified revenue, margin, and FCF impacts give you the downside number you need to decide whether the position size is appropriate.

When it matters

Before initiating or adding to any semiconductor position at or near cycle peak conditions, defined as book-to-bill above 1.1 and channel inventory below historical averages.

Investor take

Build the inventory correction scenario using the last comparable correction in the company's history as the template. What happened to revenue, gross margin, and FCF in 2019, 2015, or 2008? Apply those percentage moves to current-period financials and compare the resulting trough numbers to what the current valuation implies.

Evidence

Semiconductor cycle scorecard

The signals that tell you where you are in the cycle before earnings do

These metrics move before revenue and margin do. Reading them together is the difference between entering at the bottom of a correction and buying into the peak.

Book-to-Bill Ratio
Orders / Shipments
A ratio above 1.0 means demand exceeds current supply. Below 1.0 means orders are slower than shipments — a leading indicator of inventory build. The SIA publishes a monthly book-to-bill for the industry; company-level disclosures are often more revealing when tracked quarterly.
Channel Inventory Days
Distributor & OEM inventory / COGS run rate
The single most predictive correction indicator. When distributor days on hand expand beyond their 5-year average, the supply chain is absorbing inventory before placing new orders. A 20-day excess over normal translates to roughly 3-4 quarters of revenue headwind for the chip supplier.
Wafer Starts / Capacity Utilization
Active capacity as % of rated capacity
For foundries and IDMs, utilization above 90% compresses lead times and expands gross margin. Below 80%, fixed-cost under-absorption can push gross margins down 5-10 percentage points from peak. The inflection from declining to recovering utilization is often the best entry point for IDM stocks.
Lead Times
Weeks from order to delivery
Expanding lead times signal tight supply and typically precede ASP increases and customer double-ordering. Compressing lead times signal oversupply and typically precede order cancellations and price pressure. Watch for when customers stop disclosing lead times — they often do this when conditions are normalizing and they want to reduce negotiating pressure.
Gross Margin vs. Utilization
GM delta per utilization point
For high-fixed-cost manufacturers, each 1% drop in utilization below 85% typically costs 30-60 basis points of gross margin. Know the fixed-cost absorption ratio for any IDM or foundry you own. It tells you how quickly margins compress in a downcycle and how fast they recover when utilization comes back.
Design Wins (Pipeline Coverage)
Revenue from new design wins vs. current revenue
A design win locks a chip into a customer's product for the life of that product — often 3-5 years. A strong design-win pipeline provides revenue visibility independent of the current inventory cycle. Fabless companies with 2x+ pipeline-to-current-revenue coverage are less exposed to near-term cycle weakness.

Business model comparison

Semiconductor business models are not interchangeable — the valuation lens must match the economics

Applying the same P/E multiple to a fabless designer and an IDM is one of the most common valuation errors in semiconductor coverage.

Semiconductor business models are not interchangeable — the valuation lens must match the economics
Business modelPrimary valuation lensKey metrics to anchorStructural risk to understand
Fabless (NVDA, AMD, Qualcomm)P/E or EV/FCF at normalized marginsGross margin trajectory, design-win pipeline, R&D as % of revenueFoundry dependency: a TSMC capacity shortage or pricing change directly impacts margins with no operational offset.
Integrated Device Manufacturer (TI, ADI, Intel)EV/EBITDA or P/FCF through the cycleGross margin at trough utilization, ROIC vs. WACC, capex as % of revenueFixed-cost structure: when utilization drops from 90% to 70%, gross margin compresses rapidly and FCF can turn negative without demand recovery.
Foundry (TSMC, GlobalFoundries)EV/EBITDA or EV/Sales at mid-cycle revenueCapacity utilization by node, ASP per wafer, capex commitment vs. customer pre-paymentConcentration: the top 5 customers often represent 60%+ of revenue, and a platform shift by one hyperscaler or smartphone OEM changes the demand picture.
Semiconductor Equipment (AMAT, LRCX, ASML)EV/Sales or P/E on shipment-normalized revenueBook-to-bill for equipment, WFE spend guidance from foundries, service revenue mixCapital spending cycles: equipment revenue lags foundry and IDM capex decisions by 6-18 months, creating an amplified version of the chip cycle in the equipment names.

Common mistake

Buying on current EPS during an upcycle is not a valuation — it is a cycle bet without cycle discipline

When book-to-bill is above 1.2 and lead times are extended, reported gross margins often sit 5-10 percentage points above mid-cycle levels because of pricing power and full utilization. Applying a historical P/E multiple to those peak earnings produces a price target that is 30-50% above fair value on normalized economics. The correction arrives when channel inventory normalizes, not when management guides down. By the time the guide-down lands, the stock has already moved. The discipline is to always underwrite what the business earns through a full cycle, not what it earns at the peak.

Common questions

What investors ask about investor foundations for investor foundations stocks.

What is the most important metric for analyzing a semiconductor stock?
Book-to-bill ratio and channel inventory days together. Book-to-bill above 1.0 means incoming orders exceed shipments — a leading indicator of pricing power and demand. Channel inventory days tells you whether the existing supply chain is lean or building. When book-to-bill is falling and channel inventory is rising simultaneously, a revenue and margin correction is typically 1-3 quarters away, regardless of what guidance says.
How do you value a semiconductor company through an inventory cycle?
Anchor on mid-cycle normalized earnings, not the peak print. Estimate what gross margins look like at 75-80% utilization (neither peak nor trough), back into a normalized operating margin, and apply a through-cycle P/E multiple consistent with the business's historical ROIC spread over its cost of capital. For equipment companies, EV/Sales at mid-cycle revenue is a useful cross-check. Never underwrite a position on peak-cycle EPS without explicitly modeling the correction.
What causes semiconductor earnings to surprise to the downside?
Channel inventory builds are the most predictable cause of negative surprise. When end demand softens, OEMs and distributors first draw down existing inventory before placing new orders, creating a demand air pocket that shows up in shipment volumes and then in ASPs as suppliers compete for remaining bookings. The second most common cause is underestimating the fixed-cost absorption effect: when wafer starts or equipment utilization drops from 95% to 70%, gross margins can fall 8-12 percentage points even with flat ASPs.
Fabless vs IDM: which produces better long-run returns?
Fabless companies historically generate higher ROIC because they outsource capital-intensive manufacturing to foundries, concentrating investment in R&D and design where returns are highest. IDMs carry higher capital intensity but can capture more margin per chip when process technology is differentiated. The answer depends on the competitive moat: if the IDM's process node is genuinely differentiated (Intel historically, Analog Devices in mixed-signal), the vertical integration can justify the capital. If the process is commoditized, the fixed cost base becomes a structural drag on returns.

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